1. Field of the Invention
The present invention relates to a ferroelectric semiconductor memory device and, more particularly, to a ferroelectric semiconductor memory device including a plurality of ferroelectric memory cells, each cell including a ferroelectric capacitor and a transistor connected thereto.
2. Description of the Related Art
JP 10-255483 A describes, as one of the semiconductor memory devices, a ferroelectric memory that is referred to as a TC parallel unit series-connected ferroelectric memory (also referred to as “Chain type FeRAM”). The TC parallel unit series-connected ferroelectric memory includes a plurality of ferroelectric memory cells, each cell including a ferroelectric capacitor and a transistor connected thereto.
The conventional TC parallel unit series-connected ferroelectric memory, which is a ferroelectric memory, writes information to the ferroelectric memory cell by a combination of erasing written information and writing new information. The ferroelectric memory cell should thus be erased before being written with new information. Because the cell should be erased in advance, writing information to the ferroelectric memory cell takes too much time. This is an obstacle to a high-speed writing, i.e., a rapid storage to the semiconductor memory device.
The ferroelectric memory needs to increase and decrease a voltage of a plate line used to erase and write information. Unfortunately, the plate line is connected to a ferroelectric capacitor having a large capacitance and a transistor diffusion layer and the like. The plate line thus has a large capacity, thereby taking a long time to increase and decrease the potential of the plate line. Further, a large amount of data needs to be written to the ferroelectric memory by repeatedly erasing and writing data every time the data is written to the memory. This requires increase and decrease of the plate line potential every data write, thus making it difficult to provide a high-speed writing.